/**
 @file sys_usw_dmps_shared_reg.c

 @author  Copyright (C) 2022 Centec Networks Inc.  All rights reserved.

 @date 2022-11-08

 @version v1.0

*/

/// TEMP COMMENT
/// mcmac_reg.c content :

/****************************************************************************
 *
* Header Files
*
****************************************************************************/
#include "drv_api.h"
#include "usw/include/drv_common.h"
#include "ctc_error.h"
#include "sys_usw_dmps_reg.h"
#include "sys_usw_dmps_shared_reg.h"
#include "sys_usw_datapath.h"
#include "sys_usw_dmps_db.h"
#include "sys_usw_dmps_drv_def.h"


extern sal_file_t g_tm_dump_fp;
extern uint8 g_dmps_dbg_sw;

#define DRV_IOW_FIELD_NZ(core_id, pp_id, dp_id, lchip, memid, inst_id, fieldid, value, ptr) \
    do\
    {\
        int32 retv = 0;\
        char   fld_str[64] = {0};\
        retv = drv_set_field(lchip, memid, fieldid, ptr, value);\
        if (retv < 0)\
        {\
            return(retv); \
        }\
        drv_usw_get_field_string_by_id(lchip, memid, fieldid, fld_str);\
        if ((NULL != g_tm_dump_fp) && (g_dmps_dbg_sw))\
        {\
            if ((255 != pp_id) && (255 != dp_id))\
            {\
                sal_fprintf(g_tm_dump_fp, "write %-35s 0 %-45s 0x%x inst %-5d core %u pp %u dp %u\n", \
                TABLE_NAME(lchip, memid), fld_str, *value, inst_id, core_id, pp_id, dp_id); \
            }\
            else if ((255 != pp_id))\
            {\
                sal_fprintf(g_tm_dump_fp, "write %-35s 0 %-45s 0x%x inst %-5d core %u pp %u\n", \
                TABLE_NAME(lchip, memid), fld_str, *value, inst_id, core_id, pp_id); \
            }\
            else\
            {\
                sal_fprintf(g_tm_dump_fp, "write %-35s 0 %-45s 0x%x inst %-5d core %u\n", \
                TABLE_NAME(lchip, memid), fld_str, *value, inst_id, core_id); \
            }\
        }\
    }\
    while(0)

#define DRV_IOW_ENTRY(lchip, memid, inst_id, entry_id, fieldid, value, ptr) \
    do\
    {\
        int32 retv = 0;\
        char   fld_str[64] = {0};\
        retv = drv_set_field(lchip, memid, fieldid, ptr, value);\
        if (retv < 0)\
        {\
            return(retv); \
        }\
        drv_usw_get_field_string_by_id(lchip, memid, fieldid, fld_str);\
        if ((NULL != g_tm_dump_fp) && (g_dmps_dbg_sw))\
        {\
            sal_fprintf(g_tm_dump_fp, "write %-35s %-5d %-45s 0x%x inst %-5d\n", \
                TABLE_NAME(lchip, memid), entry_id, fld_str, *value, inst_id); \
            sal_fflush(g_tm_dump_fp);\
        }\
    }\
    while(0)

#define DRV_IOW_ENTRY_NZ(core_id, pp_id, dp_id, lchip, memid, inst_id, entry_id, fieldid, value, ptr) \
    do\
    {\
        int32 retv = 0;\
        char   fld_str[64] = {0};\
        retv = drv_set_field(lchip, memid, fieldid, ptr, value);\
        if (retv < 0)\
        {\
            return(retv); \
        }\
        drv_usw_get_field_string_by_id(lchip, memid, fieldid, fld_str);\
        if ((NULL != g_tm_dump_fp) && (g_dmps_dbg_sw))\
        {\
            if ((255 != pp_id) && (255 != dp_id))\
            {\
                sal_fprintf(g_tm_dump_fp, "write %-35s %-5d %-45s 0x%x inst %-5d core %u pp %u dp %u\n", \
                    TABLE_NAME(lchip, memid), entry_id, fld_str, *value, inst_id, core_id, pp_id, dp_id); \
            }\
            else if ((255 != pp_id))\
            {\
                sal_fprintf(g_tm_dump_fp, "write %-35s %-5d %-45s 0x%x inst %-5d core %u pp %u\n", \
                    TABLE_NAME(lchip, memid), entry_id, fld_str, *value, inst_id, core_id, pp_id); \
            }\
            else\
            {\
                sal_fprintf(g_tm_dump_fp, "write %-35s %-5d %-45s 0x%x inst %-5d core %u\n", \
                    TABLE_NAME(lchip, memid), entry_id, fld_str, *value, inst_id, core_id); \
            }\
            sal_fflush(g_tm_dump_fp);\
        }\
    }\
    while(0)


#define ______WRITE_SHARED_REGISTER_API______
int32
sys_usw_dmps_shared_reg_write_quad_sgmac_cfg(uint8 lchip, uint8 core_id, uint8 inst_id,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = QuadSgmacCfg_t;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 value   = 0;
    QuadSgmacCfg_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);
    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        switch (fld_info[fld_idx].field_id)
        {
            case QuadSgmacCfg_cfgQuadSgmacRxBufMode_f:
            case QuadSgmacCfg_cfgQuadSgmacTxBufMode_f:
            case QuadSgmacCfg_cfgQuadSgmacTxBufParityEn_f:
            case QuadSgmacCfg_cfgSgmacTxPauseMacSaHi_f:
                fld_id = fld_info[fld_idx].field_id;
                break;
            case QuadSgmacCfg_cfgSgmac0TxBufRst_f:
                dmps_QuadSgmacCfg_cfgSgmac0TxBufRst_f(fld_info[fld_idx].idx, fld_id);
                break;
            case QuadSgmacCfg_cfgSgmac0PausePulseSel_f:
                dmps_QuadSgmacCfg_cfgSgmac0PausePulseSel_f(fld_info[fld_idx].idx, fld_id);
                break;
            default:
                fld_id = DMPS_INVALID_VALUE_U32;
                break;
        }

        value  = fld_info[fld_idx].value;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, inst_id, fld_id, &value, &shared_reg);
    }

    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_write_sgmac_tx_cfg(uint8 lchip, uint8 core_id, uint8 inst_id, uint8 tbl_idx,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = 0;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 value   = 0;
    Sgmac0TxCfg_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    dmps_Sgmac0TxCfg_t(tbl_idx, tbl_id);
    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {

        fld_id = fld_info[fld_idx].field_id;
        value  = fld_info[fld_idx].value;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, inst_id, fld_id, &value, &shared_reg);
    }

    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_write_sgmac_rx_cfg(uint8 lchip, uint8 core_id, uint8 inst_id, uint8 tbl_idx,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = 0;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 value   = 0;
    Sgmac0RxCfg_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    dmps_Sgmac0RxCfg_t(tbl_idx, tbl_id);
    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {

        fld_id = fld_info[fld_idx].field_id;
        value  = fld_info[fld_idx].value;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, inst_id, fld_id, &value, &shared_reg);
    }

    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_write_sharedmii0cfg(uint8 lchip, uint8 core_id, uint8 inst_id, uint8 tbl_idx,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = 0;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 value   = 0;
    SharedMii0Cfg_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    dmps_SharedMii0Cfg_t(tbl_idx, tbl_id);
    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        fld_id = fld_info[fld_idx].field_id;
        value  = fld_info[fld_idx].value;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, inst_id, fld_id, &value, &shared_reg);
    }

    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_write_shared_mii_cfg(uint8 lchip, uint8 core_id, uint8 inst_id,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = SharedMiiCfg_t;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 value   = 0;
    SharedMiiCfg_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        fld_id = fld_info[fld_idx].field_id;
        value  = fld_info[fld_idx].value;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, inst_id, fld_id, &value, &shared_reg);
    }

    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_write_shared_pcs_cfg(uint8 lchip, uint8 core_id, uint8 inst_id,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = SharedPcsCfg_t;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 value   = 0;
    SharedPcsCfg_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        switch (fld_info[fld_idx].field_id)
        {
            case SharedPcsCfg_cgMode_f:
            case SharedPcsCfg_xlgMode_f:
            case SharedPcsCfg_rxauiMode_f:
            case SharedPcsCfg_xauiMode_f:
                fld_id = fld_info[fld_idx].field_id;
                break;
            case SharedPcsCfg_lgMode0_f:
                dmps_SharedPcsCfg_lgMode0_f((fld_info[fld_idx].idx / 2), fld_id);
                break;
            case SharedPcsCfg_fxMode0_f:
                dmps_SharedPcsCfg_fxMode0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case SharedPcsCfg_sgmiiModeRx0_f:
                dmps_SharedPcsCfg_sgmiiModeRx0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case SharedPcsCfg_sgmiiModeTx0_f:
                dmps_SharedPcsCfg_sgmiiModeTx0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case SharedPcsCfg_unidirectionEn0_f:
                dmps_SharedPcsCfg_unidirectionEn0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case SharedPcsCfg_xxvgMode0_f:
                dmps_SharedPcsCfg_xxvgMode0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case SharedPcsCfg_halfDuplexEn0_f:
                dmps_SharedPcsCfg_halfDuplexEn0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case SharedPcsCfg_halfDuplexMode0_f:
                dmps_SharedPcsCfg_halfDuplexMode0_f(fld_info[fld_idx].idx, fld_id);
                break;
            default:
                fld_id = DMPS_INVALID_VALUE_U32;
                break;
        }

        value  = fld_info[fld_idx].value;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, inst_id, fld_id, &value, &shared_reg);
    }

    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_write_shared_pcs_fec_cfg(uint8 lchip, uint8 core_id, uint8 inst_id,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = SharedPcsFecCfg_t;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 value   = 0;
    SharedPcsFecCfg_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        switch (fld_info[fld_idx].field_id)
        {
            case SharedPcsFecCfg_cgfecEn_f:
            case SharedPcsFecCfg_xlgPcsFecEn_f:
                fld_id = fld_info[fld_idx].field_id;
                break;
            case SharedPcsFecCfg_lgPcsFecRsMode0_f:
                dmps_SharedPcsFecCfg_lgPcsFecRsMode0_f(fld_info[fld_idx].idx / 2, fld_id);
                break;
            case SharedPcsFecCfg_lgPcsFecEn0_f:
                dmps_SharedPcsFecCfg_lgPcsFecEn0_f(fld_info[fld_idx].idx / 2, fld_id);
                break;
            case SharedPcsFecCfg_xfiPcsFecEn0_f:
                dmps_SharedPcsFecCfg_xfiPcsFecEn0_f(fld_info[fld_idx].idx, fld_id);
                break;
            default:
                fld_id = DMPS_INVALID_VALUE_U32;
                break;
        }

        value  = fld_info[fld_idx].value;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, inst_id, fld_id, &value, &shared_reg);
    }

    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_write_xg_fec_ctl_shared_fec(uint8 lchip, uint8 core_id, uint8 inst_id, uint8 tbl_idx,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = 0;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 value   = 0;
    XgFec0CtlSharedFec_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    dmps_XgFec0CtlSharedFec_t(tbl_idx, tbl_id);
    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        fld_id = fld_info[fld_idx].field_id;
        value  = fld_info[fld_idx].value;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, inst_id, fld_id, &value, &shared_reg);
    }

    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_write_global_ctl_shared_fec(uint8 lchip, uint8 core_id, uint8 inst_id,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = GlobalCtlSharedFec_t;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 value   = 0;
    GlobalCtlSharedFec_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        switch (fld_info[fld_idx].field_id)
        {
            case GlobalCtlSharedFec_cfgSharedFec40GPort_f:
            case GlobalCtlSharedFec_cfgSharedFec100GPort_f:
            case GlobalCtlSharedFec_cfgSharedFecLane0And3SwapEn_f:
                fld_id = fld_info[fld_idx].field_id;
                break;
            case GlobalCtlSharedFec_cfgSharedFec50GPort0RsMode_f:
                dmps_GlobalCtlSharedFec_cfgSharedFec50GPort0RsMode_f(fld_info[fld_idx].idx / 2, fld_id);
                break;
            case GlobalCtlSharedFec_cfgSharedFec50GPort0_f:
                dmps_GlobalCtlSharedFec_cfgSharedFec50GPort0_f(fld_info[fld_idx].idx / 2, fld_id);
                break;
            case GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f:
                dmps_GlobalCtlSharedFec_cfgSharedFec25GPort0RsMode_f(fld_info[fld_idx].idx, fld_id);
                break;
            case GlobalCtlSharedFec_cfgSharedFecRxWidth0_f:
                dmps_GlobalCtlSharedFec_cfgSharedFecRxWidth0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f:
                dmps_GlobalCtlSharedFec_cfgSharedFecRxAmInterval0_f(fld_info[fld_idx].idx, fld_id);
                break;
            default:
                fld_id = DMPS_INVALID_VALUE_U32;
                break;
        }

        value  = fld_info[fld_idx].value;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, inst_id, fld_id, &value, &shared_reg);
    }

    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_read_shared_mii_reset_cfg(uint8 lchip, uint8 core_id, uint8 inst_id,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = SharedMiiResetCfg_t;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 value   = 0;
    uint32 step    = 0;
    SharedMiiResetCfg_m shared_reg;

    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        CTC_PTR_VALID_CHECK(fld_info + fld_idx);

        fld_id = fld_info[fld_idx].field_id;
        switch(fld_id)
        {
            case SharedMiiResetCfg_cfgSoftRstRx0_f:
                step   = SharedMiiResetCfg_cfgSoftRstRx1_f - SharedMiiResetCfg_cfgSoftRstRx0_f;
                fld_id = SharedMiiResetCfg_cfgSoftRstRx0_f + step * fld_info[fld_idx].idx;
                break;
            case SharedMiiResetCfg_cfgSoftRstTx0_f:
                step   = SharedMiiResetCfg_cfgSoftRstTx1_f - SharedMiiResetCfg_cfgSoftRstTx0_f;
                fld_id = SharedMiiResetCfg_cfgSoftRstTx0_f + step * fld_info[fld_idx].idx;
                break;
            default:
                fld_id = DMPS_INVALID_VALUE_U32;
                break;
        }
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &value, &shared_reg);

        fld_info[fld_idx].value = value;
    }

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_write_shared_mii_reset_cfg(uint8 lchip, uint8 core_id, uint8 inst_id,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = SharedMiiResetCfg_t;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 value   = 0;
    SharedMiiResetCfg_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        switch (fld_info[fld_idx].field_id)
        {
            case SharedMiiResetCfg_cfgSoftRstRx0_f:
                dmps_SharedMiiResetCfg_cfgSoftRstRx0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case SharedMiiResetCfg_cfgSoftRstTx0_f:
                dmps_SharedMiiResetCfg_cfgSoftRstTx0_f(fld_info[fld_idx].idx, fld_id);
                break;
            default:
                fld_id = DMPS_INVALID_VALUE_U32;
                break;
        }

        value  = fld_info[fld_idx].value;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, inst_id, fld_id, &value, &shared_reg);
    }

    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_write_shared_pcs_soft_rst(uint8 lchip, uint8 core_id, uint8 inst_id,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = SharedPcsSoftRst_t;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 value   = 0;
    SharedPcsSoftRst_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        switch (fld_info[fld_idx].field_id)
        {
            case SharedPcsSoftRst_rxDeskewSoftRstLg_f:
            case SharedPcsSoftRst_rxDeskewSoftRst_f:
            case SharedPcsSoftRst_rxXauiDeskewSoftRst0_f:
            case SharedPcsSoftRst_rxXauiDeskewSoftRst1_f:
            case SharedPcsSoftRst_softRstCgTx_f:
            case SharedPcsSoftRst_softRstCgRx_f:
            case SharedPcsSoftRst_softRstXlgTx_f:
            case SharedPcsSoftRst_softRstXlgRx_f:
            case SharedPcsSoftRst_softRstLgTx_f:
            case SharedPcsSoftRst_softRstLgRx_f:
                fld_id = fld_info[fld_idx].field_id;
                break;
            case SharedPcsSoftRst_softRstPcsRx0_f:
                dmps_SharedPcsSoftRst_softRstPcsRx0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case SharedPcsSoftRst_softRstPcsTx0_f:
                dmps_SharedPcsSoftRst_softRstPcsTx0_f(fld_info[fld_idx].idx, fld_id);
                break;
            default:
                fld_id = DMPS_INVALID_VALUE_U32;
                break;
        }

        value  = fld_info[fld_idx].value;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, inst_id, fld_id, &value, &shared_reg);
    }

    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_write_reset_ctl_shared_fec(uint8 lchip, uint8 core_id, uint8 inst_id,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = ResetCtlSharedFec_t;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 value   = 0;
    ResetCtlSharedFec_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        switch (fld_info[fld_idx].field_id)
        {
            case ResetCtlSharedFec_cfgSoftRstFecRx0_f:
                dmps_ResetCtlSharedFec_cfgSoftRstFecRx0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case ResetCtlSharedFec_cfgSoftRstFecTx0_f:
                dmps_ResetCtlSharedFec_cfgSoftRstFecTx0_f(fld_info[fld_idx].idx, fld_id);
                break;
            default:
                fld_id = DMPS_INVALID_VALUE_U32;
                break;
        }

        value  = fld_info[fld_idx].value;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, inst_id, fld_id, &value, &shared_reg);
    }

    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_write_shared_pcs_dsf_cfg(uint8 lchip, uint8 core_id, uint8 inst_id,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = SharedPcsDsfCfg_t;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 value   = 0;
    SharedPcsDsfCfg_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        switch (fld_info[fld_idx].field_id)
        {
            case SharedPcsDsfCfg_cfgDsfDepth0_f:
                //step   = SharedPcsDsfCfg_cfgDsfDepth1_f - SharedPcsDsfCfg_cfgDsfDepth0_f;
                //fld_id = SharedPcsDsfCfg_cfgDsfDepth0_f + step * (fld_info[fld_idx].idx / 2);
                dmps_SharedPcsDsfCfg_cfgDsfDepth0_f(fld_info[fld_idx].idx / 2, fld_id); ///TODO:index not sure
                break;
            case SharedPcsDsfCfg_forceRealign0_f:
                //step   = SharedPcsDsfCfg_forceRealign1_f - SharedPcsDsfCfg_forceRealign0_f;
                //fld_id = SharedPcsDsfCfg_forceRealign0_f + step * (fld_info[fld_idx].idx / 2);
                dmps_SharedPcsDsfCfg_forceRealign0_f(fld_info[fld_idx].idx / 2, fld_id);
                break;
            case SharedPcsDsfCfg_forceRxLane0_f:
                //step   = SharedPcsDsfCfg_forceRxLane1_f - SharedPcsDsfCfg_forceRxLane0_f;
                //fld_id = SharedPcsDsfCfg_forceRxLane0_f + step * (fld_info[fld_idx].idx / 2);
                dmps_SharedPcsDsfCfg_forceRxLane0_f(fld_info[fld_idx].idx / 2, fld_id);
                break;
            case SharedPcsDsfCfg_forceRxLane0Num_f:
                dmps_SharedPcsDsfCfg_forceRxLane0Num_f(fld_info[fld_idx].idx, fld_id);
                break;
            default:
                fld_id = DMPS_INVALID_VALUE_U32;
                break;
        }

        value  = fld_info[fld_idx].value;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, inst_id, fld_id, &value, &shared_reg);
    }

    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_write_shared_pcs_serdes_cfg(uint8 lchip, uint8 core_id, uint8 inst_id, uint8 tbl_idx,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = 0;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 value   = 0;
    SharedPcsSerdes0Cfg_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    dmps_SharedPcsSerdes0Cfg_t(tbl_idx, tbl_id);
    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        fld_id = fld_info[fld_idx].field_id;
        value  = fld_info[fld_idx].value;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, inst_id, fld_id, &value, &shared_reg);
    }

    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_write_shared_pcs_sgmii_cfg(uint8 lchip, uint8 core_id, uint8 inst_id, uint8 tbl_idx,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = 0;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 value   = 0;
    SharedPcsSgmii0Cfg_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    dmps_SharedPcsSgmii0Cfg_t(tbl_idx, tbl_id);
    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        fld_id = fld_info[fld_idx].field_id;
        value  = fld_info[fld_idx].value;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, inst_id, fld_id, &value, &shared_reg);
    }

    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_write_shared_pcs_xlg_cfg(uint8 lchip, uint8 core_id, uint8 inst_id, uint8 tbl_idx,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = SharedPcsXlgCfg_t;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 value   = 0;
    SharedPcsSgmii0Cfg_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        fld_id = fld_info[fld_idx].field_id;
        value  = fld_info[fld_idx].value;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, inst_id, fld_id, &value, &shared_reg);
    }

    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_write_quad_sgmac_init(uint8 lchip, uint8 core_id, uint8 inst_id,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = QuadSgmacInit_t;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 value   = 0;
    QuadSgmacInit_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        fld_id = fld_info[fld_idx].field_id;
        value  = fld_info[fld_idx].value;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, inst_id, fld_id, &value, &shared_reg);
    }

    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_write_quad_sgmac_stats_cfg(uint8 lchip, uint8 core_id, uint8 inst_id,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = QuadSgmacStatsCfg_t;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    uint32 value   = 0;
    QuadSgmacStatsCfg_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        fld_id = fld_info[fld_idx].field_id;
        value  = fld_info[fld_idx].value;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOW_FIELD_NZ(core_id, 0xff, 0xff, lchip, tbl_id, inst_id, fld_id, &value, &shared_reg);
    }

    cmd    = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    return CTC_E_NONE;
}






#define ______READ_SHARED_REGISTER_API______

int32
sys_usw_dmps_shared_reg_read_sharedmii0status(uint8 lchip, uint8 core_id, uint8 inst_id, uint8 tbl_idx,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = 0;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    SharedMii0Status_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    dmps_SharedMii0Status_t(tbl_idx, tbl_id);
    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        fld_id = fld_info[fld_idx].field_id;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &(fld_info[fld_idx].value), &shared_reg);
    }

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_read_shared_pcs_sgmii_status(uint8 lchip, uint8 core_id, uint8 inst_id, uint8 tbl_idx,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = 0;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    SharedPcsSgmii0Status_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    dmps_SharedPcsSgmii0Status_t(tbl_idx, tbl_id);
    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        fld_id = fld_info[fld_idx].field_id;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &(fld_info[fld_idx].value), &shared_reg);
    }

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_read_shared_pcs_xfi_status(uint8 lchip, uint8 core_id, uint8 inst_id, uint8 tbl_idx,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = 0;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    SharedPcsXfi0Status_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    dmps_SharedPcsXfi0Status_t(tbl_idx, tbl_id);
    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        fld_id = fld_info[fld_idx].field_id;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &(fld_info[fld_idx].value), &shared_reg);
    }

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_read_shared_pcs_xlg_status(uint8 lchip, uint8 core_id, uint8 inst_id,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = SharedPcsXlgStatus_t;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    SharedPcsXlgStatus_m shared_reg;

    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        CTC_PTR_VALID_CHECK(fld_info + fld_idx);

        fld_id = fld_info[fld_idx].field_id;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &(fld_info[fld_idx].value), &shared_reg);
    }

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_read_shared_pcs_lg_status(uint8 lchip, uint8 core_id, uint8 inst_id,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = SharedPcsLgStatus_t;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    SharedPcsLgStatus_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        fld_id = fld_info[fld_idx].field_id;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &(fld_info[fld_idx].value), &shared_reg);
    }

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_read_shared_pcs_cg_status(uint8 lchip, uint8 core_id, uint8 inst_id,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = SharedPcsCgStatus_t;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    SharedPcsCgStatus_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        fld_id = fld_info[fld_idx].field_id;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &(fld_info[fld_idx].value), &shared_reg);
    }

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_read_shared_pcs_fx_status(uint8 lchip, uint8 core_id, uint8 inst_id, uint8 tbl_idx,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = 0;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    SharedPcsFx0Status_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    dmps_SharedPcsFx0Status_t(tbl_idx, tbl_id);
    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        fld_id = fld_info[fld_idx].field_id;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &(fld_info[fld_idx].value), &shared_reg);
    }

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_read_fc2112_fec_count(uint8 lchip, uint8 core_id, uint8 inst_id, uint8 tbl_idx,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = 0;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    XgFec0StatusSharedFec_m fc2112_fec;

    CTC_PTR_VALID_CHECK(fld_info);

    dmps_XgFec0StatusSharedFec_t(tbl_idx, tbl_id);
    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &fc2112_fec));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        fld_id = fld_info[fld_idx].field_id;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &(fld_info[fld_idx].value), &fc2112_fec);
    }

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_read_sharedmii0cfg(uint8 lchip, uint8 core_id, uint8 inst_id, uint8 tbl_idx,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = 0;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    SharedMii0Cfg_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    dmps_SharedMii0Cfg_t(tbl_idx, tbl_id);
    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        fld_id = fld_info[fld_idx].field_id;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &(fld_info[fld_idx].value), &shared_reg);
    }

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_read_shared_pcs_sgmii_cfg(uint8 lchip, uint8 core_id, uint8 inst_id, uint8 tbl_idx,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = 0;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    SharedPcsSgmii0Cfg_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    dmps_SharedPcsSgmii0Cfg_t(tbl_idx, tbl_id);
    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        fld_id = fld_info[fld_idx].field_id;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &(fld_info[fld_idx].value), &shared_reg);
    }

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_read_shared_pcs_cfg(uint8 lchip, uint8 core_id, uint8 inst_id, 
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = SharedPcsCfg_t;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    SharedPcsCfg_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        switch (fld_info[fld_idx].field_id)
        {
            case SharedPcsCfg_cgMode_f:
            case SharedPcsCfg_xlgMode_f:
            case SharedPcsCfg_rxauiMode_f:
            case SharedPcsCfg_xauiMode_f:
                fld_id = fld_info[fld_idx].field_id;
                break;
            case SharedPcsCfg_lgMode0_f:
                dmps_SharedPcsCfg_lgMode0_f((fld_info[fld_idx].idx / 2), fld_id);
                break;
            case SharedPcsCfg_fxMode0_f:
                dmps_SharedPcsCfg_fxMode0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case SharedPcsCfg_sgmiiModeRx0_f:
                dmps_SharedPcsCfg_sgmiiModeRx0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case SharedPcsCfg_sgmiiModeTx0_f:
                dmps_SharedPcsCfg_sgmiiModeTx0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case SharedPcsCfg_unidirectionEn0_f:
                dmps_SharedPcsCfg_unidirectionEn0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case SharedPcsCfg_xxvgMode0_f:
                dmps_SharedPcsCfg_xxvgMode0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case SharedPcsCfg_halfDuplexEn0_f:
                dmps_SharedPcsCfg_halfDuplexEn0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case SharedPcsCfg_halfDuplexMode0_f:
                dmps_SharedPcsCfg_halfDuplexMode0_f(fld_info[fld_idx].idx, fld_id);
                break;
            default:
                fld_id = DMPS_INVALID_VALUE_U32;
                break;
        }

        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &(fld_info[fld_idx].value), &shared_reg);
    }

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_read_sgmac_rx_cfg(uint8 lchip, uint8 core_id, uint8 inst_id, uint8 tbl_idx,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = 0;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    Sgmac0RxCfg_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    dmps_Sgmac0RxCfg_t(tbl_idx, tbl_id);
    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        fld_id = fld_info[fld_idx].field_id;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &(fld_info[fld_idx].value), &shared_reg);
    }

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_read_sgmac_tx_cfg(uint8 lchip, uint8 core_id, uint8 inst_id, uint8 tbl_idx,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = 0;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    Sgmac0TxCfg_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    dmps_Sgmac0TxCfg_t(tbl_idx, tbl_id);
    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        fld_id = fld_info[fld_idx].field_id;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &(fld_info[fld_idx].value), &shared_reg);
    }

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_read_shared_mii_soft_rst(uint8 lchip, uint8 core_id, uint8 inst_id,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = SharedMiiResetCfg_t;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    SharedMiiResetCfg_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        switch (fld_info[fld_idx].field_id)
        {
            case SharedMiiResetCfg_cfgSoftRstRx0_f:
                dmps_SharedMiiResetCfg_cfgSoftRstRx0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case SharedMiiResetCfg_cfgSoftRstTx0_f:
                dmps_SharedMiiResetCfg_cfgSoftRstTx0_f(fld_info[fld_idx].idx, fld_id);
                break;
            default:
                fld_id = DMPS_INVALID_VALUE_U32;
                break;
        }

        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &(fld_info[fld_idx].value), &shared_reg);
    }

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_read_shared_pcs_soft_rst(uint8 lchip, uint8 core_id, uint8 inst_id, 
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = SharedPcsSoftRst_t;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    SharedPcsSoftRst_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        switch (fld_info[fld_idx].field_id)
        {
            case SharedPcsSoftRst_rxDeskewSoftRstLg_f:
            case SharedPcsSoftRst_rxDeskewSoftRst_f:
            case SharedPcsSoftRst_rxXauiDeskewSoftRst0_f:
            case SharedPcsSoftRst_rxXauiDeskewSoftRst1_f:
            case SharedPcsSoftRst_softRstCgTx_f:
            case SharedPcsSoftRst_softRstCgRx_f:
            case SharedPcsSoftRst_softRstXlgTx_f:
            case SharedPcsSoftRst_softRstXlgRx_f:
            case SharedPcsSoftRst_softRstLgTx_f:
            case SharedPcsSoftRst_softRstLgRx_f:
                fld_id = fld_info[fld_idx].field_id;
                break;
            case SharedPcsSoftRst_softRstPcsRx0_f:
                dmps_SharedPcsSoftRst_softRstPcsRx0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case SharedPcsSoftRst_softRstPcsTx0_f:
                dmps_SharedPcsSoftRst_softRstPcsTx0_f(fld_info[fld_idx].idx, fld_id);
                break;
            default:
                fld_id = DMPS_INVALID_VALUE_U32;
                break;
        }

        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &(fld_info[fld_idx].value), &shared_reg);
    }

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_read_rs_fec_status_shared_fec(uint8 lchip, uint8 core_id, uint8 inst_id, uint8 tbl_idx,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = 0;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    RsFec0StatusSharedFec_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    dmps_RsFec0StatusSharedFec_t(tbl_idx, tbl_id);
    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        fld_id = fld_info[fld_idx].field_id;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &(fld_info[fld_idx].value), &shared_reg);
    }

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_read_global_status_shared_fec(uint8 lchip, uint8 core_id, uint8 inst_id,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = GlobalStatusSharedFec_t;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    GlobalStatusSharedFec_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        switch (fld_info[fld_idx].field_id)
        {
            case GlobalStatusSharedFec_dbgSharedFecAlignStatus0_f:
                dmps_GlobalStatusSharedFec_dbgSharedFecAlignStatus0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case GlobalStatusSharedFec_dbgSharedFecAmLock0_f:
                dmps_GlobalStatusSharedFec_dbgSharedFecAmLock0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case GlobalStatusSharedFec_dbgSharedFecPmaLane0_f:
                dmps_GlobalStatusSharedFec_dbgSharedFecPmaLane0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case GlobalStatusSharedFec_dbgSharedFecRxDskFsm0_f:
                dmps_GlobalStatusSharedFec_dbgSharedFecRxDskFsm0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case GlobalStatusSharedFec_dbgSharedFecRxOverrun0_f:
                dmps_GlobalStatusSharedFec_dbgSharedFecRxOverrun0_f(fld_info[fld_idx].idx, fld_id);
                break;
            case GlobalStatusSharedFec_dbgSharedFecRxSyncFsm0_f:
                dmps_GlobalStatusSharedFec_dbgSharedFecRxSyncFsm0_f(fld_info[fld_idx].idx, fld_id);
                break;
            default:
                fld_id = DMPS_INVALID_VALUE_U32;
                break;
        }

        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &(fld_info[fld_idx].value), &shared_reg);
    }

    return CTC_E_NONE;
}

int32
sys_usw_dmps_shared_reg_read_shared_pcs_serdes_cfg(uint8 lchip, uint8 core_id, uint8 inst_id, uint8 tbl_idx,
                                        uint8 fld_num, reg_field_info_t* fld_info)
{
    uint8  fld_idx = 0;
    uint32 tbl_id  = 0;
    uint32 fld_id  = 0;
    uint32 index   = 0;
    uint32 cmd     = 0;
    SharedPcsSerdes0Cfg_m shared_reg;

    CTC_PTR_VALID_CHECK(fld_info);

    dmps_SharedPcsSerdes0Cfg_t(tbl_idx, tbl_id);
    index  = DRV_INS(inst_id, 0);
    cmd    = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DMPS_DRV_IOCTL_CORE(lchip, index, core_id, cmd, &shared_reg));

    for (fld_idx = 0; fld_idx < fld_num; fld_idx++)
    {
        fld_id = fld_info[fld_idx].field_id;
        SYS_CONDITION_CONTINUE(DMPS_INVALID_VALUE_U32 == fld_id);
        DRV_IOR_FIELD(lchip, tbl_id, fld_id, &(fld_info[fld_idx].value), &shared_reg);
    }

    return CTC_E_NONE;
}

